Design And Reuse

»Made in Germany« Security Chip Serves as a Root of Trust for Connected Devices

With the RISC-V Secure Element, the Fraunhofer Institutes for Integrated Circuits IIS, for Applied and Integrated Security AISEC, and for Electronic Microsystems and Solid State Technologies EMFT are ...
Design And Reuse

Ultra-low jitter, low spurious tones, LC-based PLL-10GHz

INCIRT’s APLL10GGF22 is an LC-oscillator-based charge-pump PLL that provides ultra-low jitter (Integrated RMS jitter: 150 fs, integrated from 1 kHz ...
Design And Reuse

TW330 - Advanced Image warping IP (Distortion Correction IP)

Integrating advanced on-the-fly coordinate transformation and image processing powered by GPU technologies - High-performance image warping IP ...
Design And Reuse

Ceva Wins Landmark AI Licensing Deal with Major U.S. Software and AI Platform Company

NeuPro-M chosen as NPU IP foundation for custom AI silicon program, enabling OS-to-silicon optimization for next-generation intelligent computing devices ROCKVILLE, Md. — Ceva, Inc. (NASDAQ: CEVA), ...
Design And Reuse

TAKUMI starts licensing new Warping IPs "TW270" and "TW290"

TAKUMI Corporation (Head Office: 4-3-6 Shiba, Minato-ku, Tokyo; President & CEO: Osamu Shigenami) today announced the start of licensing for two new Warping IP (Distortion correction IP) products, ...
Design And Reuse

SkyeChip Advances Custom Interface IP Engagement with Cerebras for Wafer-Scale AI Platforms

SkyeChip Berhad (“SkyeChip”), a Bursa Malaysia-listed silicon IP and silicon products company, today announced its ongoing engineering engagement with Cerebras Systems Inc. (Nasdaq: CBRS), a global AI ...
Design And Reuse

CAST Licenses TCP/IP Hardware Stack Core for Keysight FieldFox Handheld Spectrum Analyzers

CAST, a leading provider of high-performance semiconductor IP cores, today announced that Keysight Technologies has licensed CAST’s 1G/10G TCP/IP Hardware Stack IP core for integration into its ...
Design And Reuse

High-Speed SerDes Design: Architecture, Equalization, and CDR Circuits

High-Speed Serializer/Deserializer (SerDes) technology addresses these challenges by enabling efficient communication over ...
Design And Reuse

Discuss Silicon-Ready UCIe IP at DAC 2026, Long Beach, California

T2M, a leading provider of high-performance semiconductor IP cores, today announced the availability of its partner’s advanced UCIe Die-to-Die Interface IP core, a scalable digital interconnect ...
Design And Reuse

Electronics Digital Twin platform from Synopsys for accelerating physical AI development

Open platform enables seamless integrations with a comprehensive technology ecosystem and cloud‑based deployment. By engineerlive.com. Synopsys has launched the Synopsys Electro ...
Design And Reuse

Microsoft accelerates quantum-safe timeline for adoption by 2029

Microsoft Azure CTO, Mark Russinovich has announced that the organization is now accelerating its Quantum Safe Program (QSP) with the goal of transitioning products and services to PQC by 2029. It’s a ...
Design And Reuse

Chips&Media to Supply APV IP for Future Google Smartphones

Chips&Media will supply its Advanced Professional Video (APV) intellectual property (IP) to Google for the first time, marking the company's entry into Google's smartphone ecosystem. The IP is ...